| RTL Signal | GLS Signal | Width | Match | Match % | Status | 1st Diverge |
|---|
Each mapped signal is compared independently across aligned clock edges. Unlike whole-state fingerprinting (v2), individual bit-level faults are never drowned out by clean signals. Divergences are classified as faults (persistent, >5 consecutive edges) or transients (self-recovering glitches).
Faulty signals are grouped by causal relationship (RTLAID graph fan-out analysis) or timing proximity (fallback). The earliest-diverging signal in each group is identified as the root cause; later divergences are symptoms — downstream propagation of the same fault.
A fast hash-based fingerprint confirms overall VCD consistency. If Layer 1 reports all signals clean but the fingerprint diverges, it indicates unmapped signals carrying faults — reported as WARNING. Status: FAIL
RTL and GLS signals are matched using 4 strategies: exact name match (confidence 1.0), basename match (0.9), Verilog-escaped match (0.85), and flattened hierarchy match (0.7). Width validation ensures bus widths agree. Verified mappings are cached for subsequent runs. This run: 346 mappings (cached).
Mode: wildcard. In wildcard mode, X/Z values match anything (common in GLS where uninitialized memory produces X before first write). In strict mode, X only matches X. In zero mode, X is treated as 0.
RTL and GLS simulations may have different edge counts due to clock gating or reset timing. Anchor-based alignment uses value transitions to match edges across the two VCDs, tolerating up to 5 edges of skew. Alignment achieved: 100.0%.